Particular embodiments generally relate to regulators for conversion of voltages.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Regulators, such as buck regulators, may be used to generate a lower direct current (DC) voltage from a higher DC voltage. For example, FIG. 1 depicts an example of a conventional buck regulator. The buck regulator includes an inductor 104, a capacitor 106, and a load 108. Switches 102a and 102b may be opened and closed to either charge inductor current or discharge inductor current. For example, when switch 102a is closed and switch 102b is open, input supply is applied across the inductor 104 to charge the current. Also, when switch 102a is open and switch 102b is closed, the voltage polarity across inductor 104 is reversed and the current is discharged. The inductor current is distributed between capacitor 106 and load 108.
An input supply voltage is applied across inductor 104 to charge the inductor current when the output voltage (Vout) is below a reference voltage (Vref). When the inductor current is higher than the load current, the excess current charges capacitor 106 causing the output voltage to rise towards the reference voltage. When the output voltage goes above the reference voltage, the voltage polarity across inductor 104 is reversed and the inductor current decays. When the inductor current is lower than the load current, the deficit current is supplied from capacitor 106 causing the output voltage to decrease towards the reference voltage.
A control system may be used to determine when to open and close switches 102a and 102b. The output voltage is compared to the reference voltage at a comparator 110. In one example, if the output voltage is above the reference voltage, comparator 110 outputs a low logic value (e.g., ‘0’) and if the output voltage is below the reference voltage, comparator 110 outputs a high logic value (e.g., ‘1’). A flip-flop 112, such as a D flip-flop, receives the comparator output signal, Compout. When clocked using a clock signal CLKIN, flip-flop 112 outputs the comparator output signal to a selector 114.
Selector 114 receives two signals DC1 and DC2 with different duty cycles, a duty cycle DC1 and a duty cycle DC2. The duty cycle DC1 has a duty cycle that is less than the duty cycle DC2. Depending on the value of the comparator output received at S0, either signal DC1 or signal DC2 is selected and output to a pre-driver 116. For example, if the comparator output signal is ‘0’, signal DC1 is selected, and if the comparator output signal is ‘1’, the signal DC2 is selected. Thus, the duty cycle is higher when the output voltage is above the reference voltage and the duty cycle is lower when the output voltage is below the reference voltage.
Depending on the duty cycle of the signal, pre-driver 116 controls switches 102a and 102b differently. The duty cycle of signals DC1 and DC2 determines how much current is either charged or discharged from/to inductor 104 for a percentage of time. For example, when the signals DC1 and DC2 are high, switch 102a is closed and switch 102b is open, and when the signals DC1 and DC2 are low, switch 102a is open and switch 102b is closed. However, since DC2 has a higher duty cycle than DC1, the time signal DC2 is high is greater than the time signal DC1 is high. Thus, switch 102a is closed longer when DC2 is input to pre-driver 116 than when DC1 is provided to pre-driver 116.
The output voltage may include what is sometimes referred to as a ripple. Ripple is systematic fluctuations in the output voltage over time. Ripple may be caused by two factors: a phase lag between a current through inductor 104 and the resulting output voltage or as a consequence of a nonzero value of an equivalent series resistance (ESR) of capacitor 106 or an additional external ESR added in series with capacitor 106. A larger value for the ESR reduces the phase lag. However, the larger value for the ESR increases the ripple in the output voltage. Also, when the ESR value is reduced to zero, a maximum phase lag occurs, which increases the ripple in the output voltage.
A designer should choose the value of the ESR to maximize performance. However, the control is included on an integrated circuit (IC) chip while capacitor 106 is external to the IC (e.g., off chip). Thus, a designer of the control may not be able to control what value of the ESR inherent to capacitor 106 or added in series to capacitor 106. This may reduce the performance of the regulator because the value for the ESR is not within the control of the designer and may not be optimized for maximum performance.